1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with remedying means for defective memory cells.
2. Description of the Related Art
A semiconductor memory device such as a DRAM (Dynamic Random Access Memory) is provided with respective memory cells at intersection points of a plurality of pairs of bit lines and a plurality of word lines. In this semiconductor memory device, the word line is selected with a row address and the pair of bit lines is selected with a column address to thereby allow the stored information of an intended memory cell to be read.
A conventional semiconductor memory device such as a DRAM employs a scheme of dividing a storage area into a plurality of blocks for an increased storage capacity or due to limitations on the length of the pair of bit lines.
For reading stored information stored in a memory cell of a semiconductor memory device comprising such a plurality of blocks, a row address is first specified, then a column address is specified and a block address must be specified. After the addresses are specified, a command is provided from the outside, thereby performing various operations such as data writing or reading.
However, even if the semiconductor memory device comprises a plurality of blocks as described above, there exists a problem that an increased storage capacity and an increased number of blocks require a long time for reading the stored content when one block can not be processed while another block is being processed.
For solving this problem, a synchronous DRAM and the like have come into use in which memory cells are divided into banks which can operate independent of each other, not dividing the memory cells into a plurality of blocks.
Within each bank, a group of memory cells specified with an address signal applied from the outside are activated. At this time, respective banks can be simultaneously in an activated state. The addresses of the group of memory cells to be activated are independent among the respective banks.
FIG. 1 shows a configuration of a conventional semiconductor memory device comprising such a plurality of banks.
In this figure, description is made assuming that the number of banks is two [bank A (ARRAY0) and bank B (ARRAY1)], the number of subarrays forming each bank is four (SA00 to SA03, SA10 to SA13, respectively), and the number of subword lines (not shown) included in each subarray is 512. Also, description is made here by using a hierarchy word lines structure. In this case, the number of the subword lines are eight for one main word line MWL. Thus, the row address of each bank comprises 11 bits (X0 to X10). Each subarray in each bank is identified by bits X9, X10, each main word line in each subarray is identified by bits X3 to X8, and each of eight subword line for one main word line is identified by bits X0 to X2.
The replacement of a defective memory cell with a redundant memory cell is performed by two row addresses designated by bit X0. Each subarray has one redundant main word line RMWL (Redundant MWL) and eight subword lines connected thereto.
FIGS. 2A and 2B show timing charts illustrating the operation of this conventional semiconductor memory device. FIG. 2A is a timing chart when the redundant memory cell is selected, while FIG. 2B is a timing chart when the redundant memory cell is not selected. ACT in FIGS. 2A and 2B denotes a signal indicating that a bank corresponding to each ACT is in an activated state, and is generated by a command decoder (not shown) and the like in response to a command input from the outside.
In FIG. 1, XADD comprising 11 bits is a row address signal and is fetched from the outside in accordance with ACT signal by an address buffer (not shown). XABF denotes a row address signal buffer circuit and generates complementary signals X1N to X10N, X1T to X10T in accordance with X1 to X10 within row address signals XADD. Respective redundant decoders XRED are circuits which store respective defective addresses to be replaced and perform storage/comparison for defective addresses.
FIG. 3 is a circuit diagram showing an example of redundant decoder XRED as described above. Redundant decoder XRED compares row address signal XADD and the defective address stored therein.
In this conventional semiconductor memory device, the replacement is made with two subword lines as a unit, so that X1 to X10 making up row address signal XADD are stored. Subword lines designated by X0, for example row address 0 and row address 1 are not distinguished within redundant decoder XRED and are determined as defective addresses when either of them is applied to redundant decoder XRED.
In redundant decoder XRED, the replacement address is stored by disconnecting either of fuses F1N to F10N or F1T to F10T. Although the way of disconnecting the fuse is not particularly limited, fusion with laser beam is commonly used. Disconnection of either FnN or FnT causes one bit of the replacement address to be stored. For example, when the relevant bit in the replacement address is 0 or 1, F1N to F10N are disconnected and F1T to F10T are not disconnected.
Next, the operation of redundant decoder XRED will be described. First, all of row address signal XADD go to a low level and redundant precharge signal PXR goes to a low level, thereby causing node 100 to go to a high level. Subsequently, based on an address signal applied from the outside, the states X1N to X10N and X1T and X10T are set within the complementary signals of 11 bits making up row address signal XADD. At this time, since XnN and XnT (n=1 to 10) are complementary signals, one of them is at a high level and the other is at a low level. For example, when the row address is 0 or 1, X1N to X10N are at a high level and X1T to X10T are at a low level. Thus, node 100 and node 101 are rendered conductive unless the replacement address stored in fuses FnN, FnT and row address signal XADD match.
Node 100 goes to a low level when redundant precharge signal PXR goes to a high level and the replacement address and row address signal XADD do not match, and node 100 remains at a high level when they match. Level at node 100 is held at node 102 in response to latch signal XLAT and outputted as defective address match signal XREBL. FIG. 2A shows a case where the replacement address and row address signal XADD match and defective address match signal XREBL at a high level is outputted. FIG. 2B shows a case where the replacement address and row address signal XADD do not match and defective address match signal XREBL at a low level is outputted.
When ACT signal goes to a low level, all defective address match signals XREBL are made unselected in response to XPRE signal as shown in FIGS. 2A and 2B, and therefore the selected redundant memory cell is made unselected.
FIG. 4 is a circuit diag ram showing an example of redundant memory cell selection circuit XRDN.
Redundant memory cell selection circuit XRDN exists on a one-to-one basis for each redundant row decoder RXDC. Since one redundant decoder XRED exists for two subword lines, one redundant memory cell selection 25 circuit XRDN exists for four redundant decoders XRED. This ratio is equal to the ratio of the number of the main word lines to the number of the subword lines. Redundant memory cell selection circuit XRDN, when one of four defective address match signals XREBL connected thereto goes to a high level, causes redundant replacement selection signal XRDNS set at a high level by a precharge circuit (not shown) to be pulled down to a low level. Redundant replacement selection signal XRDNS is a signal indicating that the redundant memory cell has been selected. Also, redundant memory cell selection circuit XRDN causes redundant row decoder selection signal RXDS to go to at a high level, and activates redundant row decoder RXDC connected on a one-to-one basis.
Additionally, redundant subword line selection signals RRAIS1, RRAIS2, set at a high level by a precharge circuit (not shown), are selectively pulled down to a low level in response to defective address match signal XREBL. RRAIS1, RRAIS2 are not pulled down to a low level when XREBL0 goes to a high level among four defective address match signals XREBL0 to XREBL3 connected to the redundant memory cell selection circuit XRDN. However, only RRAIS1 is pulled down when XREBL1 goes to a high level, only RRAIS2 is pulled down when XREBL2 goes to a high level, and both of redundant subword line selection signals RRAIS1, RRAIS2 are pull down when XREBL3 goes to a high level. Therefore, the comparison result in redundant decoder XRED matches the state of redundant subword line selection signal RRAIS signal.
Redundant decoder XRED and redundant memory cell selection circuit XRDN are fixed with respect to a bank to which each of them belongs and operate only when the relevant bank is selected. Also, each signal of redundant precharge signal PXR, latch signal XLAT, XPRE, redundant row decoder selection signal RXDS, redundant replacement selection signal XRDNS exists independently for each bank and operates independently.
XPR in FIG. 1 denotes a row address predecoder which generates row address predecode signal PXADD from row address signal XADD, as shown in FIGS. 2A and 2B. It is to be noted that row address predecode signal PXADD comprises eight signals including X3N, X4N, X5N to x3T, X4T, X5T obtained through predecoding X3 to X5, eight signals including X6N, X7N, X8N to X6T, X7T, X8T obtained through predecoding X6 to X8, and four signals including X9N, X10N to X9T, X10T obtained through predecoding X9, X10. Eight signals including X3T, X4T, X5T and so on and eight signals including X6T, X7T, X8T and so on are used for selecting row decoder XDEC in each subarray, while four signals including X9T, X10T and so on are used for selecting the subarray in SXC circuit. Row predecode address signal PXADD is delayed within row address decode circuit XPR in order to wait for determination whether the redundant memory cell is selected or not, and latched by latch signal XLAT signal. When ACT signal goes to a low level, all row predecode address signals PXADD are made unselected by XPRE signal. As a result, the selected memory cell is made unselected.
FIG. 5 is a circuit diagram showing an example of subarray selection circuit SXC. When row address signal XADD does not match any of the redundant defective replacement addresses stored in redundant decoders XRED and redundant row decoder selection signal RXDS remains at a high level, subarray selection circuit SXC activates a sense amplifier array, (not shown) included in the relevant subarray, and activates subarray selection signal BSEL, based on row predecode address signal PXADD (X9, X10).
When row address signal XADD matches any one of the defective replacement addresses stored in redundant decoders XRED and redundant row decoder selection signal RXDS goes to a low level, subarray selection circuit SXC activates a sense amplifier array based on redundant replacement selection signal XRDNS and activates subarray selection signal BSED. At this time, when the subarray indicated by row predecode address signal PXADD and the subarray indicated by redundant replacement selection signal XRDNS do not match, the redundant main word line and the sense amplifier array within the subarray indicated by row predecode address signal PXADD are inhibited to be activated. In any case, the sense amplifier array to be activated is included in the subarray containing the activated word line.
FIG. 6 is a circuit diagram showing an example of row decoder XDEC. Row decoder XDEC activates main word line MWL based on row predecode address signal PXADD (X3 to X8) and subarray selection signal BSEL. However, when row address signal XADD matches any one of the replacement addresses stored in redundant decoders XRED and the redundant row decoder selection signal goes to a low level, the activation will not be performed.
FIG. 7 is a circuit diagram showing an example of redundant row decoder RXDC. When row address signal XADD matches any of the replacement addresses stored in redundant decoders XRED, redundant row decoder RXDC will activate the corresponding redundant main word line RMWL based on redundant replacement selection signal XRDNS. Thus, a main word line including a defective address will be replaced with a redundant main word line.
FIG. 8 is a circuit diagram showing an example of subword line selection circuit RAIS. When row address signal XADD does not match any of the defective replacement addresses of redundant decoders XRED and redundant row decoder selection signal RXDS is at a high level, subword line selection circuit RAIS will activate only one of subword line selection signals RAI0 to RAI7 in accordance with row address signal XADD (X0 to X2). On the other hand, when row address signal XADD matches one of the defective replacement addresses of redundant decoders XRED and redundant row decoder selection signal RXDS is at a low level, redundant subword line selection signal RRAIS1 instead of X1 of row address signal XADD, redundant subword line selection signal RRAIS2 instead of X2, and X0 of row address signal XADD are used to select one of subword line selection signals RAI0 to RAI7. Main word line MWL and subword line selection signal RAI are applied to a subword driver circuit (not shown), and an AND logic of these signals is used to select subword line SWL. Subword line SWL is directly connected to the memory cell to activate the memory cell.
As described above, in this prior art, the relationship of redundant decoder XRED, the main word line activated thereby, and subword line selection signal RAI is fixed, which results in a fixed relationship of each redundant decoder XRED and the subword line. Also, the number of the subword lines (two in this case) to which one redundant decoder XRED is responsible for replacement is also fixed.
In this case, there exist four redundant main word lines per bank and 32 relevant subword lines. 16 redundant decoders XRED exist within one bank. Since the replacement by one redundant decoder XRED is performed with two subword lines having an address only differing in X0 as a unit, up to 16 defective points per bank can be remedied if each of all defective points has either only one row address or two addresses only differing in X0.
However, if each defective point does not have two addresses only differing in X0, for example if the main word line (corresponding to eight subword lines having an address only differing in X0 to X2) is defective, four redundant decoders XRED are used for replacement with eight subword lines. In this case, 16 redundant decoders XRED per bank can be used to remedy four main word lines. In any case, redundant decoder XRED circuit and redundant subword line used for the defect replacement are used only within each bank and are not used for the defect replacement of another banks.
However, in the aforementioned semiconductor memory device, for example when a defective memory cell physically existing in bank B is replaced with a redundant memory cell physically existing in bank A, two memory cells may be simultaneously activated in bank A if the redundant memory cell in bank A replacing the defective memory cell in bank B is to be activated at a timing which activates bank A. When these memory cells share a sense amplifier, a data line and so on, malfunction would occur. Since the addresses of two memory cells in different banks can be specified independently and optionally from the outside, this problem can not be avoided for all combinations of addresses.
Therefore, in the semiconductor memory device having a configuration such as shown in FIG. 1, it is impossible to remedy by sharing a redundant memory cell among different banks, so that a defective memory cell in each bank can be replaced only with the redundant memory cell in the same bank. Therefore, for a chip where defects locally exist in some banks, the whole chip can not be remedied at a time when a defective memory cell can not be replaced with a redundant memory cell even in one bank, which leads to a prime cause of reducing the yield.
Also, since cut of fuses with laser imposes a limitation on a finer fuse, a redundant decoder generally requires a larger area as compared with other circuits. Thus, the maximum number of redundant memory cells that can be provided is determined by the number of the redundant decoders that can be provided.
A semiconductor memory device has different patterns for the address arrangement of defective bits in terms of the structure and method of fabricating. These defective patterns are classified into a defective pattern which can be remedied by the replacement of one row address, such as a single bit defect caused by an element such as a transistor making up a memory cell and a single line defect caused by disconnection of a wiring in a memory cell array, and a defective pattern which can be remedied by replacement of a plurality of row addresses, such as a row decoder circuit defect and an adjacent lines defect caused by shorts among wirings in a memory cell array.
Also, even in a case where replacement of a plurality of lines is required, the number of adjacent row addresses requiring replacement is indefinite since it depends on the amount of dust accumulated during the step, which leads to a primary cause of shorts among wirings. Therefore, since in the prior art replacement of a defect for a fixed number of the row addresses is performed by one redundant decoder, a plurality of redundant decoders are needed to perform the replacement when the number of adjacent defective row addresses exceeds a replacement unit. Conversely, if the number of adjacent defective row addresses is below the replacement unit, replacement is performed including indefective the row address, adjacent to defective row address, thereby reducing the efficiency of using redundant memory cell.
In the conventional semiconductor memory devices, a redundancy decoder associated with one bank is capable of replacing only a defective memory cell in the bank with a redundant memory cell. Therefore, the banks need respective redundancy decoders. As a result, the efficiency with which to replace defective memory cells with redundant memory cells is low, resulting in a poor yield.